A metal oxide semiconductor field effect transistor (MOSFET) is used in forming dynamic random access memory (DRAM) cells. A DRAM circuit typically includes an array of memory cells interconnected by rows and columns, which are known as wordlines and bitlines, respectively. Reading data from, or writing data to, memory cells is achieved by activating selective wordlines and bitlines. Typically, a DRAM cell comprises a MOSFET connected to a capacitor. The capacitor includes two electrodes that are separated by a node dielectric, while the MOSFET includes a gate and diffusion regions that are referred to as either the source or drain region, depending on the operation of the transistor.
There are different types of MOSFETs known to those skilled in the art. A planar MOSFET is a transistor where a surface of the channel region of the transistor is generally parallel to the primary surface of the substrate. A vertical MOSFET is a transistor where a surface of the channel region of the transistor is perpendicular to the primary surface of the substrate. A trench MOSFET is a transistor where a surface of the channel region of the transistor is not parallel to the primary surface of the substrate and the channel region lies within the substrate. For a trench MOSFET, the surface of the channel region is usually perpendicular to the primary surface, although this is not required.
Trench capacitors are frequently employed with DRAM cells. A trench capacitor is a three-dimensional structure formed into a Si-containing substrate. This is normally formed by etching trenches of various dimensions into the Si-containing substrate. Trenches commonly have N+doped polysilicon as one electrode of the capacitor (i.e., the storage node) and the other electrode of the capacitor is a buried plate that is formed via out-diffusion of dopants into a portion of the substrate surrounding the lower portion of the trench.
A typical trench storage memory cell is shown, for example, in FIG. 1. Specifically, the trench capacitor memory cell of FIG. 1 comprises substrate 10 having N+ bitline diffusion regions 12 formed therein. The substrate also includes a plurality of trench capacitor memory cells 14. Each trench capacitor memory cell includes trench capacitor 16 formed in a lower portion of the trench and vertical MOSFET 18 formed in an upper portion of the trench. The trench capacitor includes N+ buried plate diffusion 20 formed about the exterior walls of the trench, node dielectric 22 lining the interior walls of the trench, and storage capacitor node conductor 24 formed within the trench on the exposed walls of the node dielectric.
The vertical MOSFET includes gate dielectric 26 formed on vertical sidewalls of the trench, and gate conductor 28 formed on the gate dielectric. The trench capacitors and the vertical MOSFET are isolated from each other by trench top oxide layer 30 and collar isolation oxide 32, yet the structures are in electrical communication through N+ buried strap diffusion region 34.
In addition to providing device isolation between the vertical MOSFET and the trench capacitor, the collar oxide 32 also provides a means to prevent current leakage from the vertical parasitic transistor 36 that exists on the sidewalls of the trench between the N+ buried strap diffusion regions and the N+ buried plate diffusion region.
One problem with the current processing flow is that collar oxide formation requires extra processing steps to define the length of the collar oxide. The extra processing steps required in the prior art for collar oxide formation increase the fabrication time as well as the cost. Moreover, in instances in which high aspect ratio trenches are employed, the thickness of conventional collar oxides makes it difficult to completely fill the lower regions of the trenches with a storage node conductor.
In view of the above drawbacks with the prior art, there is a continued need for providing a simple means for forming collar isolation for trench capacitor memory cells that can be integrated relatively easily into existing DRAM processes.